1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More specifically, the present invention relates to a method of forming a compressive channel layer of a p-type metal oxide semiconductor (PMOS) device and to a PMOS device having a compressive channel layer.
2. Description of the Related Art
As semiconductor devices become more highly integrated and the speed of the semiconductor device increases, a thinner gate oxide layer and a higher driving current are beneficial. However, as the size of the device is reduced, a gate voltage may be reduced, and a driving current may be reduced in proportion to the gate voltage and/or a breakdown voltage of a gate dielectric. Under certain conditions, the device performance may be degraded due to an increased incidence of hot carrier injection (HCI). This may occur when the size of the device is reduced, but the voltage applied to the gate of the device is not proportionately reduced.
In order to solve the problem, a method of improving the mobility of a carrier by applying stress to silicon has recently been developed. As a typical example, a method of using a Si—Ge layer having different lattice constant from the crystal of a silicon layer has been widely used. In this method, a Si—Ge epitaxial layer is grown on a Si substrate, and an epitaxial Si layer is grown thereon to apply stress to the upper silicon layer that constitutes the channel layer of the device. In the normal crystal structure of silicon, atoms exist at the summits of a regular hexahedral structure. Meanwhile, a compressed silicon substrate receives compressive stress in a direction parallel to the surface thereof so that the compressed silicon substrate has a modified rectangular crystal structure. When the crystal structure is compressed by external force, the electrical and physical characteristics of the silicon are changed, so that the mobility of the carrier that moves therein improves. As a result, the speed and performance of the semiconductor device are improved.
However, in order to selectively form a Si—Ge layer only in PMOS devices (that is, in order to separate the PMOS devices from n-type metal oxide semiconductor [NMOS] devices), an additional oxidation process must performed. As a result, the manufacturing process is relatively complicated, and the manufacturing cost of the semiconductor device increases. Furthermore, since the Si—Ge layer reduces the band gap of the silicon channel layer, when the semiconductor device is operated, a leakage current may increase.